The present invention relates to microelectronics, and more specifically to a structure and method for providing an air gap for enhancing performance of an on-chip passive device overlying a semiconductor region of a semiconductor integrated circuit chip.
Techniques exist for providing passive devices, e.g., inductors, capacitors and/or resistors in a layer or region of an integrated circuit chip which overlies a semiconductor region in which active devices are provided. However, the performance of inductors and capacitors on such chips can be constrained by the type of dielectric material that is used to isolate their conductive portions from other features of the chip. For example, in the prior art chip illustrated in FIGS. 1A-1B, an inductor 10 includes a metal feature or other conductive feature which extends in a spiral pattern within a region 12 of a solid dielectric material which overlies a semiconductor region 14 of a microelectronic substrate such as a chip. The inductor 10 is provided at a level of the chip which is separated from the semiconductor region of the chip by several layers of interlevel dielectric (“ILD”) material, or ILD layers. As particularly shown in FIG. 1B, the inductor 10 is embedded in an ILD layer consisting essentially of one or more inorganic dielectric materials 18c, such as an oxide or nitride of silicon, typically silicon dioxide. An ILD layer 18b underlying the ILD layer 18c typically also consists essentially of one or more inorganic dielectric materials. A further inorganic ILD layer 18a is provided in close proximity to the semiconductor region 18a. Between the inorganic ILD layer 18a and an the inorganic ILD layer 18b immediately below the inductor 10, a stack including a plurality of organic ILD layers 20a, 20b, 20c are provided. Each of the organic ILD layers typically consists essentially of an inorganic dielectric material such as a low-K (low dielectric constant) material, e.g. SiCOH or an organic dielectric material commonly known as polyarylene(ether) (“PAE”) or SiLK™ (supplied by Dow Chemical).
Conductive metal patterns 22a, 22b, 22c, which can include a variety of metals such as copper, are used to interconnect features of the chip typically are embedded in the organic ILD layers. The low dielectric constant material of the organic ILD layers therein reduces parasitic capacitance associated by the juxtaposition of conductive metal patterns. The reduced dielectric constant material also allows the conductive metal patterns to be larger and placed at a tighter pitch than would be permitted if a dielectric material having a higher dielectric constant were used. Between each pair of immediately adjacent ILD layers a dielectric cap layer is provided, which typically includes a material which functions as a barrier to prevent diffusion of contaminating substances, especially copper, into the ILD layers, especially to protect ILD layers of SiCOH, SiLK™ or silicon oxide. Specifically, between a dielectric cap layer 24a is provided between layer 18a and layer 20a, and a dielectric cap layer 24b is provided between layer 20a, and 20b, etc. The dielectric cap layers typically consist essentially of a material such as silicon nitride or silicon carbo-nitride. A top dielectric cap layer 25 overlies the uppermost ILD layer, and a passivation layer 27 overlies the top dielectric cap layer. The top dielectric cap layer 25 typically consists essentially of silicon nitride, and the passivation layer 27 typically consists essentially of silicon dioxide.
One problem of the structure shown in FIGS. 1A and 1B is the close proximity to the inductor 10 of dielectric materials in ILD layers which do not have low dielectric constants. The relative dielectric constants of silicon dioxide and silicon nitride are approximately 4 and 7, respectively, and the dielectric constants of the low-K organic dielectric materials are well above 1.0, typically on the order of 2-3.5. The presence of the dielectric materials is a source of parasitic capacitance as well as a decrease in the “Q” factor of the inductor (a metric of the RF performance of the device), due to coupling with substrate.
Prior attempts to address this problem have led to other problems. For example as illustrated in FIG. 2, the article by C. H. Chen et al. “A Deep Submicron CMOS Process Compatible Suspending High-Q Inductor”, IEEE Elec. Dev. Lett., vol. 22, p. 523, 2001 describes an arrangement in which metal patterns 30 which form an inductor lie unsupported within an air gap 32 formed by isotropically etching a region 34 of relatively low density silicon dioxide. The silicon dioxide region 34 is exposed through a window in a layer of silicon nitride 36 overlying the silicon dioxide region 34, which in turn, overlies a relatively dense oxide region 35 such as a field oxide region overlying a semiconductor substrate 37. Other than through one stack of conductive vias 38 and horizontally disposed metal features 40, the metal patterns 30 of the inductor lie entirely unsupported.
The arrangement shown in the article by Chen is subject to various problems. The metal patterns 30 are unsupported by dielectric material, either below, above, or between individual metal lines of the inductor. Mechanical stresses such as shock and vibration, as well as thermal expansion and contraction stresses, can cause the metal lines to move relative to each other and potentially cause the metal lines to weaken or break. In addition, the process of making the air gap is not robust. Variability in the etch rate and timing of the etch process used to hollow out the air gap 32 can lead to an air gap having variable volume. This may cause the finished inductor to exhibit inconsistent performance.